1. Field of the Invention
The present invention relates to the field of flash memory integrated circuits. Specifically, the present invention relates to high-voltage circuits used for programming and erasing flash memory. The high-voltage circuits use NMOS transistors to pass internally generated high-voltages to flash memory.
2. Discussion of the Related Art
In flash memory integrated circuits, high voltages are generated on the chip for programming purposes. These high voltages (around 20V) are much higher than the highest supply voltage (around 3V), and are typically produced by large charge pumps. Because these charge pumps consume power and circuit area, it is desirable to minimize the total capacitance that these high voltage generators drive.
In most CMOS integrated circuits, PMOS transistors are used to pass the higher supply voltages, while NMOS transistors are used to pass the lower supply voltages. For example, PMOS transistors are used to implement pull up circuits, while NMOS transistors are used to implement pull down circuits. However, PMOS transistor subcircuits in a CMOS integrated circuit must be electrically isolated in an N-type well which must be biased at or above the same high voltage to guarantee that the P/N junction formed by the P-type drain/source regions of the PMOS transistors and the N-type well are not forward biased. If PMOS transistors are used in the high-voltage subcircuits, these N-type isolation wells constitute a very large capacitance for the on-chip high voltage generator to drive. Moreover, the N-type isolation well itself increases area and adds process complexity. Because NMOS transistors are typically fabricated on a P-type substrate, NMOS transistors require no isolation well. Thus, they are relatively easy to fabricate with a simple process. Therefore, in high-voltage subcircuits supplied by on-chip high-voltage generators, the use of NMOS transistors is typically preferable to the use of PMOS transistors.
However, the voltage which can be passed by an NMOS transistor is limited by the transistor's threshold voltage Vt. If a gate voltage Vg is applied to an NMOS transistor's gate, then the maximum voltage which can be passed from source to drain is Vg-Vt. If the voltage generator produces a maximum voltage Vpp (about 20V), it is desirable for transistors passing or switching that high voltage to pass Vpp without incurring the threshold voltage drop. In other words, the pass transistors should pass Vpp rather than Vpp-Vt. Therefore, in order to pass a high voltage Vpp through an NMOS device, its gate must be boosted to a voltage higher than the high voltage by at least one threshold voltage Vt, so that Vpp+Vt must be applied to the gate of the NMOS pass transistor.
A conventional circuit which is used to pass a high voltage Vpp is illustrated in FIG. 1. The circuits of the kind illustrated in FIG. 1 are very important in NAND flash memory applications, especially for decoding circuits such as block and row decoders and high-voltage multiplexers. The conventional circuits and those according to the present invention will be described in conjunction with a NAND block decoder. A NAND flash memory string has more than one floating gate storage transistor. For example, each NAND memory string may contain sixteen storage transistors. Several NAND strings may be organized into a row so as to store sixteen words of data, such that each word is independently writeable and readable. Each word includes its own word line which is connected to one control gate of a data storage transistor in each NAND string in the row. The set of sixteen words which share the same NAND strings is referred to as a block. To write or read a word within a given block, that block must be selected by a block decoder so that specific voltages can be applied to the word lines within that block.
Unfortunately, the circuit in FIG. 1 has drawbacks. The first drawback is that the circuit performance is degraded as the supply voltage Vcc decreases. Moreover, the circuit is inoperative when the supply voltage Vcc is less than the sum of the threshold voltages VtM2 and VtM3 of transistors M2 and M3, respectively. In order to pass Vpp to the output OUT, node B (attached to the gate of M3) must be boosted to Vpp+VtM3. In order for node B to be boosted to Vpp+VtM3, node A must be boosted to Vpp+VtM3+VtM2. With supply voltages Vcc around 3V, and threshold voltages above 1.5V due to the body effect, the circuit in FIG. 1 does not function properly.
In order to boost node A to Vpp+VtM3+VtM2, the following inequality must hold in which CA is the total parasitic capacitance of node A. EQU Vcc*C/(C+CA).gtoreq.VtM2+VtM3
In order for the circuit in FIG. 1 to function with low supply voltages Vcc less than or equal to 3V, transistors M2 and M3 must have very low threshold voltages VtM2 and VtM3. However, the various manners of lowering the threshold voltage of a transistor all result in larger leakage currents from source to drain when the transistor is off.
Another way to attempt to satisfy the above inequality is to increase the coupling ratio C/(C+CA) by increasing the coupling capacitor C. However, capacitors are fairly large circuit elements and increasing C increases circuit area.
Typically, the high voltage pass gate of FIG. 1 is used to drive word lines of a memory array during a high-voltage operation such as programming. The memory array may have many thousands of word lines. Often only one word is programmed while all the other words are not programmed. In this case, only one of the word lines in the selected block is raised to Vpp while the other fifteen word lines in the selected block are raised to approximately one-half of Vpp; more importantly, the word lines in all of the unselected blocks are left floating. If transistor M3 is made to be a low threshold device and is replicated once for each word line, the sum of the leakage currents in all of the words in the unselected blocks will be very high, thus placing high current demands on the high voltage charge pump and wasting a large amount of power and rise time.
As is apparent from the above discussion, a need exists for a block decoder having small circuit area, low leakage current, and fast control of high voltage pass transistors.